Conventionally, when an analog signal is processed in a digital circuit, an analog-to-digital (AD) converter for converting the analog signal into a digital signal is provided at a preceding stage of the digital circuit. For example, an AD converter provided with an oscillator that generates an oscillation signal having a frequency that depends on a signal level of an analog signal, n (n is an integer of two or more) flip-flops, and a logic circuit has been proposed (for example, refer to Non-Patent Document 1).
In the AD converter, the n flip-flops hold values of the oscillation signal at respective timings obtained by dividing an oscillation cycle of the oscillation signal into n, and supply data indicating these values to the logic circuit. Then, the logic circuit delays the data over a period of one cycle of a sampling clock, compares the data before the delay and the data after the delay on a bit basis to count the number of bits changed from “0” to “1”, and outputs a digital signal of the count value. If a change amount of a phase of the oscillation signal within the sampling period is equal to or less than a half cycle of the oscillation cycle, the count value depends on the change amount of the phase. Therefore, the digital signal has an accurate value that depends on the signal level of the analog signal.